`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:40:54 11/07/2007 
// Design Name: 
// Module Name:    RAMB16_S32 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module RAM_A10_D16(WE, EN, CLK, ADDR, DI, DO);
    input WE;
    input EN;
    input CLK;
    input [9:0] ADDR;
    input [15:0] DI;
    output [15:0] DO;
	 	 
//  RAMB16_S18 : In order to incorporate this function into the design,
//   Verilog   : the following instance declaration needs to be placed
//  instance   : in the body of the design code.  The instance name
// declaration : (RAMB16_S18_inst) and/or the port declarations within the
//    code     : parenthesis may be changed to properly reference and
//             : connect this function to the design.  All inputs
//             : and outputs must be connected.

//  <-----Cut code below this line---->

   // RAMB16_S18: Virtex-II/II-Pro, Spartan-3/3E 1k x 16 + 2 Parity bits Single-Port RAM
   // Xilinx HDL Language Template, version 9.2.1i

   RAMB16_S18 RAMB16_S18_inst (
      .DO(DO),      // 16-bit Data Output
      .DOP(int_DOP),    // 2-bit parity Output
      .ADDR(ADDR),  // 10-bit Address Input
      .CLK(CLK),    // Clock
      .DI(DI),      // 16-bit Data Input
      .DIP(2'd0),    // 2-bit parity Input
      .EN(EN),      // RAM Enable Input
      .SSR(1'b0),    // Synchronous Set/Reset Input
      .WE(WE)       // Write Enable Input
   );

   // End of RAMB16_S18_inst instantiation
							
endmodule