Lecture 1: Introduction
Lecture 2: MOS Transistors
Lecture 3: Switch and Gate Logic
Lecture 4: Circuit DC Analysis, Transient Analysis, RC Delay Models
Lecture 5: Combinational Logic and Logical Effort
Lecture 6: Interconnects and Wire Engineering
Lecture 7: Sequential Logic Design and Clocking Strategies
Lecture 8: Two-Phase Clocking Rules & Domino Logic
Lecture 9: Design Methodology
Lecture 10: Datapath Subsystems
Lecture 11: MOS Memory and Array Subsystems
Lecture 12: Impact of Variations on Embedded Memories
Lecture 13: Special-Purpose Subsystems
Lecture 14: Power & Scaling in VLSI
Supplement: The New Era of Scaling in an SoC World
(Plenary presentation by Mark Bohr (Intel) at ISSCC 2009)