Abstract

Pre-silicon function and performance modeling in the 21st century has quickly evolved, out of technology-driven necessity, into an integrated modeling art or science. No longer is it meaningful for architects to study performance (IPC) sensitivities in isolation, while product quality metrics like power, temperature and reliability are modeled only in late-stage design. With cycle-accurate performance models augmented with the burden of also projecting the above other quality-related metrics, issues related to simulation speed and analysis accuracy get magnified by a large factor. Also, increasingly, the software scaling attributes and memory queuing effects need to be modeled with greater precision than before, in projecting performance and power for large n-way systems, built out of tomorrow’s multi/many-core chips. Similarly, pre-silicon functional validation often involves factoring the effect of multiple operational modes, associated with dynamic resource management. In this tutorial, we propose to present the modern challenge of pre-silicon modeling and validation (of software-integrated multi-core systems) from the perspective of real industrial microprocessor and associated system design projects. We will also examine the techniques to model the benefits (and performance degradations) derived from on-chip power, temperature and reliability management devices within the framework of current generation multi-core integrated models. We will discuss methods of validating pre-silicon integrated models and present real data to illustrate the errors that can result from inadequate high-level abstractions during early-stage modeling. We will cover academic research concepts that have benefited or influenced industrial practice in all aspects of the above problem, and we will point to open research issues and problems that need to be solved – especially in the context of technological changes brought forth by 3D chip integration..

Organizers

Pradip Bose, IBM T. J. Watson Research Center, Yorktown Heights, NY

Patrick Bohrer, IBM Austin Research Laboratory, Austin, TX

David Brooks, School of Engineering and Applied Sciences, Harvard University, Cambridge, MA

Reference List

• D. Brooks et al., “Wattch: a framework for architecture-level power analysis and optimization,” 27th International Symposium on Computer Architecture (ISCA-27), June 2000.

• N. Vijaykrishnan et al., “Energy-driven integrated hardware-software optimizations using SimplePower,” 27th International Symposium on Computer Architecture (ISCA-27), June 2000.

• K. Skadron et al., “Temperature-Aware Microarchitecture,” 30th International Symposium on Computer Architecture (ISCA-30), June 2003.

• H. F. Hamann, P. Bose et al., “Hot-spot limited microprocessors: direct temperature and power distribution measurements,” IEEE JSSCC, vol. 42, Issue 1, January 2007.

• J. Srinivasan, S. Adve, P. Bose, J. Rivers, “The case for lifetime reliability-aware microprocessors,” 31st International Symposium on Computer Architecture (ISCA-31), June 2004.

• X. Li, S. Adve, P. Bose, J. Rivers, “SoftArch: an architecture-level tool for modeling and analyzing soft errors,” 35th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, June 2005.

• X. Li, S. Adve, P. Bose, J. Rivers, “Architecture-level soft error analysis: examining the limits of common assumptions,” 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, June 2007.

• J. Shin, V. Zyuban, P. Bose, J. Rivers, Z. Hu, “A framework for architecture-level lifetime reliability modeling,” 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, June 2007.

• V. Zyuban, D. Brooks, V. Srinivasan, P. Bose, M. Gschwind, P. Strenski, P. Emma, “Integrated power-performance optimization of processor pipelines,” IEEE Trans. Computers, August 2004.

• C. Isci et al., “An analysis of efficient multi-core global power management policies: maximizing performance for a given power budget,” 39th International Symposium on Microarchitecture (MICRO-39), December, 2006.

Contact Information

Pradip Bose (IBM Watson): pbose {at} us.ibm.com