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Design variability is one of the leading
technical challenges that impede continued technology scaling. We will
discuss the impact of design variability on next-generation microprocessor
designs in this half-day tutorial. This tutorial introduces the design
variability problem, discusses modeling approaches, and presents an
overview of existing solutions with the goal of inspiring research from
computer architects and high-level system designers. Variability takes
many forms with different spatial and temporal scales. The tutorial will
discuss three major sources of variation: process variation due to
manufacturing imperfections, voltage variability due to inductive noise,
and temperature variation due to time-varying power dissipation. Design
variability has many links to high-level architecture design: issues such
as pipeline depth, pipeline utilization and power dissipation,
cache/memory design, and multi-core architectures are tightly tied into
the variability problem. Given that the architecture research community
has familiarity and significant existing research efforts in the area of
temperature aware design, the focus of the tutorial will be on process and
voltage variability which are generally less well-understood by
architects.
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Format and Target Audience
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The tutorial will provide a soup-to-nuts overview of variation
including sources of variation, modeling techniques, design
techniques including circuit-level hooks that may be of interest to
architectural level solutions. We will draw upon our own research
experience and state-of-the art efforts by other research groups in
academia and industry.
The tutorial targets architects with interest in technology issues,
and hence we expect the audience to have a basic background in VLSI.
We expect the audience to include first and second year MS/PhD
students through senior researchers interested in learning about
this emerging research field.
The proposed tutorial brings together four researchers from industry
and academia spanning the fields of computer architecture and
circuit design. |
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Organizers
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Keith
Bowman, Intel Circuit Research Labs,
Hillsboro, Oregon
David Brooks, School of Engineering and
Applied Sciences, Harvard University, Cambridge, MA
Gu-Yeon Wei, School of Engineering and
Applied Sciences, Harvard University, Cambridge, MA
Chris
Wilkerson, Intel Circuit Research Labs, Hillsboro, Oregon |
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Topic List
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Overview of the impact of design variability
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Sources
of Variations
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Process Variations
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Voltage Variations
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Temperature Variations
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Modeling and quantifying the impact
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Process variation models (FMAX, quad-tree, etc)
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Voltage variation models (lumped, distributed)
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Temperature variation models (Hotspot, etc)
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Variations in Memory Design
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Variations in Logic Pipelines
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Design
solutions
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Additional Topics
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Reference List |
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Contact Information |
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David Brooks: dbrooks {at}
eecs.harvard.edu |
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