Tutorial @ Micro 41

Design Variability: Trends, Models, and Design Solutions

Sunday, November 9th, 2008 (morning)


Design variability is one of the leading technical challenges that impede continued technology scaling. We will discuss the impact of design variability on next-generation microprocessor designs in this half-day tutorial. This tutorial introduces the design variability problem, discusses modeling approaches, and presents an overview of existing solutions with the goal of inspiring research from computer architects and high-level system designers. Variability takes many forms with different spatial and temporal scales. The tutorial will discuss three major sources of variation: process variation due to manufacturing imperfections, voltage variability due to inductive noise, and temperature variation due to time-varying power dissipation. Design variability has many links to high-level architecture design: issues such as pipeline depth, pipeline utilization and power dissipation, cache/memory design, and multi-core architectures are tightly tied into the variability problem. Given that the architecture research community has familiarity and significant existing research efforts in the area of temperature aware design, the focus of the tutorial will be on process and voltage variability which are generally less well-understood by architects.

Format and Target Audience

The tutorial will provide a soup-to-nuts overview of variation including sources of variation, modeling techniques, design techniques including circuit-level hooks that may be of interest to architectural level solutions. We will draw upon our own research experience and state-of-the art efforts by other research groups in academia and industry.

The tutorial targets architects with interest in technology issues, and hence we expect the audience to have a basic background in VLSI. We expect the audience to include first and second year MS/PhD students through senior researchers interested in learning about this emerging research field.

The proposed tutorial brings together four researchers from industry and academia spanning the fields of computer architecture and circuit design.


Keith Bowman, Intel Circuit Research Labs, Hillsboro, Oregon

David Brooks, School of Engineering and Applied Sciences, Harvard University, Cambridge, MA

Gu-Yeon Wei, School of Engineering and Applied Sciences, Harvard University, Cambridge, MA

Chris Wilkerson, Intel Circuit Research Labs, Hillsboro, Oregon

Topic List

  • Overview of the impact of design variability

  • Sources of Variations

    • Process Variations

    • Voltage Variations

    • Temperature Variations

  • Modeling and quantifying the impact

    • Process variation models (FMAX, quad-tree, etc)

    • Voltage variation models (lumped, distributed)

    • Temperature variation models (Hotspot, etc)

  • Variations in Memory Design

    • SRAM memory (6T, 8T)

    • Dynamic memory cells (e.g. 1T, 2T, 3T1D)

    • Min Voltage issues

  • Variations in Logic Pipelines

    • Clock tuning

    • Variable latency

    • Body Bias and Voltage tuning

  • Design solutions

  • Additional Topics

    • Discussion of processor test flow

    • Aging Issues

Reference List


Contact Information

David Brooks: dbrooks {at} eecs.harvard.edu