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Reliable and efficient power delivery is critical to all types of
computing systems. As designers seek to reduce the power consumption of
systems by reducing the supply voltage, systems will begin to experience
power supply fluctuations due to the finite impedance of the power supply
network. These supply fluctuations, referred to as voltage emergencies,
must be managed by the system to provide correctness. Our research seeks
ways to handle these alarm conditions through a combined hardware/software
approach. In addition to handling these alarm conditions, we consider the
problem of voltage selection for power management. Energy-constrained
systems typically will employ dynamic voltage and frequency scaling to
match workload behavior to required performance levels – setting the
voltage/frequency to the correct level to match performance needs provides
the best energy efficiency. The advent of on-chip voltage regulators --
which our research shows has the potential to provide fast voltage
transition times and per-core voltage control -- will greatly change the
space of potential opportunities to apply DVFS. Our research explores
these issues from a hardware/software perspective in the context of future
multicore high-performance and embedded systems.
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Wonyoung Kim, David Brooks, and Gu-Yeon Wei. “A Fully-Integrated
3-Level DC-DC Converter for Nanosecond-Scale DVFS,” IEEE Journal of
Solid-State Circuits, Volume 47, No. 1, January, 2012.
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Vijay Janapa Reddi and David Brooks. “Resilient Architectures via
Collaborative Design: Maximizing Commodity Processor Performance in the
Presence of Variations,” IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, Volume 30, No. 10, October, 2011.
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Wonyoung Kim, David Brooks, and Gu-Yeon Wei. “A Fully-Integrated
3-Level DC/DC Converter for Nanosecond-Scale DVS with Fast Shunt
Regulation," IEEE International Solid-State Circuits Conference, February,
2011.
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Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael
D. Smith, Gu- Yeon Wei, David Brooks. “Voltage Noise in Production
Processors,” IEEE Micro's Top Picks in Computer Architecture Conferences,
January/February, 2011.
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Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael
D. Smith, Gu- Yeon Wei, David Brooks. “Voltage Smoothing:
Characterizing and Mitigating Voltage Noise in a Production Processor
Using Software-Guided Thread Scheduling,” 43rd International Symposium on
Microarchitecture, December, 2010. Selected as one of the Top Picks in
Computer Architecture in 2010.
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Vijay Janapa Reddi, Simone Camponani, Meeta Gupta, Michael Smith,
Gu-Yeon Wei, David Brooks, and Kim Hazelwood. “Eliminating Voltage
Emergencies via Software-Guided Code Transformations,” ACM Transactions on
Architecture and Code Optimization, Volume 7, No. 2, September, 2010.
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Vijay Janapa Reddi, Meeta S. Gupta, Glenn Holloway, Michael D. Smith,
Gu-Yeon Wei, David Brooks. “Predicting Voltage Emergencies Using
Recurring Program and Microarchitectural Activ- ity," IEEE Micro's Top
Picks in Computer Architecture Conferences, January/February, 2010.
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Meeta S. Gupta, Jude Rivers, Pradip Bose, Gu-Yeon Wei and David Brooks.
“Tribeca: Design for PVT Variations with Local Recovery and Fine-grained
Adaptation,” 42nd International Symposium on Microarchitecture, December,
2009.
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Vijay Janapa Reddi, Simone Campanoni, Meeta S. Gupta, Michael D. Smith,
Gu-Yeon Wei, and David Brooks. “Software-Assisted Hardware
Reliability: Abstracting Circuit-level Challenges to the Software Stack,”
46th Design Automation Conference (DAC), July, 2009.
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Meeta S. Gupta, Vijay Janapa Reddi, Glenn Holloway, Gu-Yeon Wei and David
Brooks. “An Event-Guided Approach to Handling
Inductive Noise in Processors,” Design, Automation, and Test in Europe
Conference (DATE-09), Nice, France, April 2009.
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Vijay Janapa Reddi, Meeta S. Gupta, Glenn Holloway, Michael D. Smith,
Gu-Yeon Wei, and David Brooks. “Voltage Emergency Prediction: A
Signature-Based Approach To Reducing Voltage Emergencies,” 15th
International Symposium on High-Performance Computer Architecture
(HPCA-15), Raleigh, NC, February, 2009.
(pdf)
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Meeta S. Gupta,
Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei, and David Brooks.
“DeCoR: A Delayed Commit and Rollback Mechanism for Handling Inductive
Noise in Microprocessors,” 14th International Symposium on
High-Performance Computer Architecture (HPCA-14), Salt Lake City, UT,
February 2008. (pdf)
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Wonyoung Kim,
Meeta S. Gupta, Gu-Yeon Wei, and David Brooks. “System Level Analysis of
Fast, Per-Core DVFS using On-Chip Switching Regulators,” 14th
International Symposium on High-Performance Computer Architecture
(HPCA-14), Salt Lake City, UT, February 2008. (pdf)
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Meeta S. Gupta,
Krishna K. Rangan, Mike D. Smith, Gu-Yeon Wei and David Brooks. “Towards
a Software Approach to Mitigate Voltage Emergencies,” International Symposium on Low Power Electronics and Design,
Portland, OR, August 2007.
(pdf)
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Meeta S. Gupta,
Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei, and David Brooks.
“Understanding Voltage Variations in Chip Multiprocessors Using a
Distributed Power-Delivery Network,” Design, Automation, and Test in
Europe Conference (DATE-07), Nice, France, April, 2007.
(pdf)
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David Hiniker, Kim Hazelwood, and Michael D. Smith.
“Improving Region Section in Dynamic Optimization Systems,”
38th International Symposium on Microarchitecture (MICRO-38), November,
2005.
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Qiang Wu, Vijay Reddi, Youfeng Wu, Jin Lee,
Dan Connors, David Brooks, Margaret Martonosi, and Douglas W. Clark.
“Dynamic Compilation Framework for
Controlling Microprocessor Energy and Performance,”
38th International Symposium on Microarchitecture (MICRO-38), November,
2005. Received Best Paper Award.
(pdf)
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Kim Hazelwood-Cettei and David Brooks.
“Eliminating Voltage Emergencies via
Microarchitectural Voltage Control Feedback and Dynamic Optimization,”
International Symposium on Low-Power Electronics and Design, August 2004.
(pdf)
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