Chip Gallery

My research focuses on technology-related design issues and their impact on computer architecture and system software. Chip prototyping provides several important benefits for this research. First, silicon implementation gives us an opportunity to learn about power and variability issues with real measurements in ways that simulations alone cannot provide. Second, our chip prototypes allow us to more convincingly demonstrate the benefits of our proposed approaches. Finally, the design process instills an appreciation of complexity, testing, and validation issues that are often not appreciated when relying only on simulation. In collaboration with Prof. Gu-Yeon Wei and the mixed-signal VLSI design group, we have designed prototype chips for several projects. We thank the SRC and UMC for fabrication support for these projects.

We have complete prototype chips for the following projects.

  • Wireless sensor network test chip, ULP-1, .18um IBM CMOS. 1st Prize in SRC SoC Design Contest. Implementation of our architecture that appears in Hempstead et al, ISCA 2005.

  • Voltage Interpolation/Variable Latency FPU test chip, .13um UMC CMOS. Measurement results appear in Liang et al, ISSCC 2008 and provides a companion to our ISCA 2008 architectural study.

  • Wireless sensor network test chip, ULP-2, .13um IBM CMOS. Successfully demonstrates wireless sensor node design with better power-performance characteristics compared to any previously published work.

The following test chips are currently under design, with tape-out planned for mid-2009...

  • Prototype on-chip voltage regulator design. Validation and prototype of our simulation-based study (Kim et al., HPCA 2008).

  • Evaluation/characterization of variations in dynamic memories.  Validation and silicon characterization of our variation-tolerant 3T1D project (Liang et al, MICRO 2007).

  • Voltage-variation tolerant design. Validation and extension of Delayed-Commit architecture for addressing voltage noise (Gupta et al., HPCA 2008).