CS246

Advanced Computer Architecture

Spring 2009

 

David Brooks

Associate Professor

Maxwell Dworkin 141
33 Oxford Street
Cambridge MA 02138
Phone: 617-495-3989
Fax: 617-495-2489

E-mail:

dbrooks {at} eecs.harvard.edu

Course Readings

Related Course


CS 141:

Computing Hardware

[Fall]




Introduction

The course will focus on the broad topic of low-power computer systems.  We'll look at environments ranging from high-performance enterprise systems down to extremely low power mobile and sensor applications with budgets in the 10s of mWs.  This will be a seminar-style course.   The class is expected to discuss and interact after reading the assigned papers.  Most of the course grade will be based on class participation and a course project.

Tentative Topics

  • Introduction to Power-Aware Computing

  • Chip/Architectural Level Power Modeling

  • Software/OS Level Power Modeling/Measurement

  • Chip and System Level Temperature Modeling

  • Newer Trends in Power-Aware Computing (di/dt, reliability,
    ultra-low-power computing, etc

  • Architectural, Compiler, and O/S Techniques to reduce
    power/temperature/etc

    • Chip/hardware level techniques

    • OS/Compiler/Software technique

    • Energy management in mobile/wireless environments

    • Energy management in hosting centers

Prerequisites

CS141 (Computing Hardware -- i.e. Basic Digital Logic/Simple Microprocessors) is required.  It would help if students have taken a junior/senior-level course in any one of Computer Architecture, Operating Systems, Compilers, or VLSI.

Course Requirements

As the course is a organized in discussion format, the major requirements are that you attend class and actively participate in the discussions.  There is a major course project at the end of the semester in the area of power-aware computer systems.  Last semester some of the projects included:

  • Measuring/analyzing power/temperature for various workloads on a Pentium4 and an XBOX system

  • Investigating architectural slack between instructions and dynamic policies to exploit slack for low-power execution

  • Developing process/technology invariant circuit-level power models and
    metrics

  • Looking at dynamic compiler/architectural interactions for di/dt control

  • Investigating the availability of bit-narrow operations in a compiler for low-power execution

Course Readings

Lecture 1 Notes

Lecture 2 Notes

Lecture 3 Notes

  • Readings: D. Brooks, P. Bose, S. Schuster, H. Jacobson, P. Kudva, A. Buyuktosunoglu, J.D. Wellman, V. Zyuban, M. Gupta, and P. Cook, “Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors,” IEEE Micro, Nov/Dec, 2000.

  • Readings: T. Mudge, “Power: A First-Class Architectural Design Constraint,” IEEE Computer, 2001.

Synthesis Lectures in Computer Architecture

Lecture 4 Notes

Lecture 5 Notes

Homework 1

Lecture 6 Notes

Lecture 7 Notes

Lecture 8 Notes

Lecture 9 readings

  • Readings: M.S. Hrishikesh, N. P. Jouppi, K. I. Farkas, D. Burger, and S.W. Keckler, P. Shivakumar, “The Optimal Useful Logic Depth per Pipeline Stage is 6 to 8 FO4 Inverter Delays,” 29th International Symposium on Computer Architecture (ISCA), June 2002.

  • Readings: Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor Zyuban, Philip N Strenski, and Philip G Emma, “Optimizing Pipelines for Power and Performance,” 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

Homework 2

Lecture 10 Notes

Lecture 11 Notes

Lecture 12 Notes

Lecture 13 Notes

Lecture 14 readings (4/8/09)

  • Readings: Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson, Kunyung Chang, “The Case for a Single-Chip Multiprocessor,” 7th International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, MA, October 1996.

Lecture 15 readings (4/13/09)

  • Readings: Changkyu Kim. Doug Burger. Stephen W. Keckler, “An Adaptive, Non-Uniform Cache Structure for. Wire-Delay Dominated On-Chip Caches,” 10th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, October 2002.

  • Readings: Sun's Niagara 2 Processor.

Lecture 16 readings (4/15/09)

  • Readings: Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei and David Brooks. “Process Variation Tolerant 3T1D-Based Cache Architectures,” 40th International Symposium on Microarchitecture (MICRO-40), Chicago, IL, December 2007.

  • Readings: Vijay Janapa Reddi, Meeta S. Gupta, Glenn Holloway, Michael D. Smith, Gu-Yeon Wei, and David Brooks. “Voltage Emergency Prediction: A Signature-Based Approach To Reducing Voltage Emergencies,” 15th International Symposium on High-Performance Computer Architecture (HPCA-15), Raleigh, NC, February, 2009.

Lecture 17 readings (4/20/09)

  • Readings: Timothy Sherwood, Suleyman Sair, and Brad Calder, “Predictor-Directed Stream Buffers,” 33rd International Symposium on Microarchitecture (MICRO-33), Monterey, CA, December 2000.

  • Readings: Rakesh Kumar, Keith Farkas, Norman Jouppi, Partha Ranganathan and Dean Tullsen, “Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction” 36th International Symposium on Microarchitecture (MICRO-36), San Diego, CA, December 2003.

Lecture 18 readings (4/22/09)

  • Readings: Xiaobo Fan, Wolf-Dietrich Weber, Luiz Andre Barroso, “Power Provisioning for a Warehouse-sized Computer,” 34th International Symposium on Computer Architecture (ISCA-34), San Diego, CA, June 2007.

  • Readings: Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan, “Larrabee: A Many-core x86 Architecture for Visual Computing,” International Conference on Computer Graphics and Interactive Techniques, Las Angeles, CA, August, 2008.

Lecture 19 readings (4/27/09)

  • Readings: Thad Starner, “Human-Powered Wearable Computing,” IBM Systems Journal, Vol. 35, No. 3 & 4, 1996.