CS246

Advanced Computer Architecture

Spring 2008

 

David Brooks

Associate Professor

Maxwell Dworkin 141
33 Oxford Street
Cambridge MA 02138
Phone: 617-495-3989
Fax: 617-495-2489

E-mail:

dbrooks {at} eecs.harvard.edu

Course Readings

Related Course


CS 141:

Computing Hardware

[Fall]




Introduction

The course will focus on the broad topic of low-power computer systems.  We'll look at environments ranging from high-performance enterprise systems down to extremely low power mobile and sensor applications with budgets in the 10s of mWs.  This will be a seminar-style course.   The class is expected to discuss and interact after reading the assigned papers.  Most of the course grade will be based on class participation and a course project.

Tentative Topics

  • Introduction to Power-Aware Computing

  • Chip/Architectural Level Power Modeling

  • Software/OS Level Power Modeling/Measurement

  • Chip and System Level Temperature Modeling

  • Newer Trends in Power-Aware Computing (di/dt, reliability,
    ultra-low-power computing, etc

  • Architectural, Compiler, and O/S Techniques to reduce
    power/temperature/etc

    • Chip/hardware level techniques

    • OS/Compiler/Software technique

    • Energy management in mobile/wireless environments

    • Energy management in hosting centers

Prerequisites

CS141 (Computing Hardware -- i.e. Basic Digital Logic/Simple Microprocessors) is required.  It would help if students have taken a junior/senior-level course in any one of Computer Architecture, Operating Systems, Compilers, or VLSI.

Course Requirements

As the course is a organized in discussion format, the major requirements are that you attend class and actively participate in the discussions.  There is a major course project at the end of the semester in the area of power-aware computer systems.  Last semester some of the projects included:

  • Measuring/analyzing power/temperature for various workloads on a Pentium4 and an XBOX system

  • Investigating architectural slack between instructions and dynamic policies to exploit slack for low-power execution

  • Developing process/technology invariant circuit-level power models and
    metrics

  • Looking at dynamic compiler/architectural interactions for di/dt control

  • Investigating the availability of bit-narrow operations in a compiler for low-power execution

Course Readings

1/30/08:

2/4/08:

2/6/08:

  • Readings: D. Brooks, P. Bose, S. Schuster, H. Jacobson, P. Kudva, A. Buyuktosunoglu, J.D. Wellman, V. Zyuban, M. Gupta, and P. Cook, “Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors,” IEEE Micro, Nov/Dec, 2000.

  • Readings: T. Mudge, “Power: A First-Class Architectural Design Constraint,” IEEE Computer, 2001.

2/11/08:

2/13/08:

2/26/08:

  • Lecture 5 Notes

  • Readings: V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, F. Baez, “Reducing Power in High-performance Microprocessors,” 35th Design Automation Conference, San Francisco, CA.

2/28/08:

3/4/08:

  • Readings: V. Zyuban and P. Strenski, “Unified Methodology for Resolving Power-Performance Tradeoffs at the Microarchitectural and Circuit Levels,” International Symposium on Low Power Electronics and Design (ISLPED-02), August 2002

  • Readings: V. Zyuban , P.N. Strenski, “Balancing Hardware Intensity in
    Microprocessor Pipelines,” IBM Journal of Research and Development, v.47
    n.5-6, p.585-598, September 2003

  • Readings: S. Gochman, R. Ronen, I. Anati, A. Berkovits, T. Kurts, A. Naveh, A. Saeed, Z. Sperber, and R.C. Valentine, “The Intel® Pentium® M Processor: Microarchitecture and Performance,” Intel Technology Journal Vol. 7 Issue 2, May 2003.

3/11/08:

  • Lecture 7 Notes

  • Readings: M.S. Hrishikesh, N. P. Jouppi, K. I. Farkas, D. Burger, and S.W. Keckler, P. Shivakumar, “The Optimal Useful Logic Depth per Pipeline Stage is 6 to 8 FO4 Inverter Delays,” 29th International Symposium on Computer Architecture (ISCA), June 2002.

  • Readings: Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor Zyuban, Philip N Strenski, and Philip G Emma, “Optimizing Pipelines for Power and Performance,” 35th International Symposium on Microarchitecture (MICRO-35), November 2002.

Homework 1

3/18/08:

  • Readings: S. Palacharla, N. P. Jouppi, and J. E. Smith, “Complexity-effective Superscalar Processors,” 24th International Symposium on Computer Architecture (ISCA), June 1997.

  • Readings: J. L. Aragon, J. Gonzalez, and A. Gonzalez, “Control Speculation for Energy-Efficient Next-Generation Superscalar Processors,” IEEE Transactions on Computers, vol. 55, no. 3, pp. 281-291, March, 2006. (Look it up in the Harvard IEEE digital library.)

4/1/08: