Multi-layer Efforts to Mitigate Process Variations

Goals

Variations in transistor device characteristics threaten to severely slow the pace of advancement in future

CMOS technology. This challenge, known as manufacturing process variations, has primarily been explored by circuit and CAD researchers. Over the past three years my research has increasingly focused on architecture and system design approaches that are resilient to device variations. 

Students

Kevin Brownell

Xiaoyao Liang

 

Variation-tolerant Pipeline Design

  • Xiaoyao Liang, Gu-Yeon Wei, and David Brooks. “ReVIVaL: Variation Tolerant Architecture Using Voltage Interpolation and Variable Latency,” IEEE Micro’s Top Picks in Computer Architecture Conferences, January/February, 2009.

  • Kevin Brownell, Gu-Yeon Wei and David Brooks. “Evaluation of Voltage Interpolation to Address Process Variations,” International Conference on Computer Aided Design (ICCAD), San Jose, CA, Nov. 2008. (pdf)

  • Gu-Yeon Wei, David Brooks, A. Durlov Khan and Xiaoyao Liang. “Instruction-driven Clock Scheduling with Glitch Mitigation,” International Symposium on Low Power Electronics and Design (ISLPED), Bangalore, India, Aug. 2008. (pdf)

  • Xiaoyao Liang, Gu-Yeon Wei, and David Brooks. “ReVIVaL: Variation Tolerant Architecture Using Voltage Interpolation and Variable Latency,” 35th International Symposium on Computer Architecture (ISCA-35), Beijing, China, June 2008. (pdf)

  • Xiaoyao Liang, David Brooks and Gu-Yeon Wei. “A Process-Variation-Tolerant Floating-point Unit with Voltage Interpolation and Variable Latency,” IEEE International Solid-State Circuits Conference (ISSCC-08), Feb. 2008. (pdf)

  • Xiaoyao Liang and David Brooks. “Mitigating the Impact of Process Variations on CPU Register File and Execution Units,” 39th International Symposium on Microarchitecture (MICRO-39), Orlando, FL, December 2006. (pdf)

  • Xiaoyao Liang and David Brooks. “Microarchitecture Parameter Selection to Optimize System Performance under Process Variation,” International Conference on Computer Aided Design (ICCAD-06), San Jose, CA, November 2006. (pdf)

  • Xiaoyao Liang and David Brooks. “Latency Adaptation for Multiported Register Files to Mitigate the Impact of Process Variations,” Workshop on Architectural Support for Gigascale Integration (ASGI-06, held in conjunction with ISCA-33),  Boston, MA, June 2006. (pdf)

 

 
Variation-tolerant Memory Design

  • Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, and David Brooks. “Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability,” IEEE MICRO’s Top Picks in Computer Architecture Conferences, January/February, 2008. (pdf)

  • Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei and David Brooks. “Process Variation Tolerant 3T1D-Based Cache Architectures,” 40th International Symposium on Microarchitecture (MICRO-40), Chicago, IL, December 2007. (pdf)

  • Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, and David Brooks. “Process Variation Tolerant Register Files Based on Dynamic Memories,” Workshop on Architectural Support for Gigascale Integration (ASGI-07, held with ISCA-34), June, 2007. (pdf)

 

Funding and Other Support

This research is supported in part by the National Science Foundation under Grant CCF-0702344 and by gifts by Intel and Sun. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation or any other sponsor.