David Brooks

Computer Science

School of Engineering and Applied Sciences

Gordon McKay Professor of

Computer Science

Maxwell Dworkin 141
33 Oxford Street
Cambridge MA 02138

Phone: 617-495-3989
Fax: 617-495-2489

E-mail:

dbrooks {at} eecs.harvard.edu

Curriculum Vitae

 

Publications

Courses

  • Simone Campanoni, Timothy M. Jones, Glenn Holloway, Gu-Yeon Wei and David Brooks. “HELIX: Making the Extraction of Thread-Level Parallelism Mainstream,” IEEE Micro, Volume 32, No. 4, July--August, 2012.

  • Michael Lyons, Gu-Yeon Wei, and David Brooks.“Shrink-Fit: A Framework for Flexible Accelerator Sizing,” IEEE Computer Architecture Letters, July--December, 2012.

  • Amanda Chih-Ning Tseng and David Brooks. “Analytical Latency-Throughput Model of Future Power Constrained Multicore Processors,” ISCA Workshop on Energy-Efficient Design (WEED), June, 2012.

  • Simone Campanoni, Timothy M. Jones, Glenn Holloway, Gu-Yeon Wei and David Brooks. “The HELIX Project: Overview and Directions,” 49th Design Automation Conference, June 2012.

  • Simone Campanoni, Timothy M. Jones, Glenn Holloway, Vijay Janapa Reddi, Gu-Yeon Wei and David Brooks. “HELIX: Automatic Parallelization of Irregular Programs for Chip Multiprocessing,” 10th International Symposium on Code Generation and Optimization (CGO), April, 2012.

  • Wonyoung Kim, David Brooks, and Gu-Yeon Wei. “A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS," IEEE Journal of Solid-State Circuits, Volume 47, No. 1, January, 2012.

  • Michael Lyons, Mark Hempstead, Gu-Yeon Wei, and David Brooks. “The Accelerator Store: A shared Memory Framework for Accelerator-based Systems," ACM Transactions on Architecture and Code Optimization, Volume 8, No. 4, January, 2012.

  • Javier Lira, Carlos Molina, David Brooks, and Antonio Gonzalez.“ Implementing a hybrid SRAM/eDRAM NUCA architecture,” 18th IEEE International Conference on High Performance Computing (HiPC), December, 2011.

  • Vijay Janapa Reddi and David Brooks. “Resilient Architectures via Collaborative Design: Maximizing Commodity Processor Performance in the Presence of Variations," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 30, No. 10, October, 2011.

  • David Brooks. “CPUs, GPUs, and Hybrid Computing," Guest Editors Note, IEEE Micro, Volume 31, No. 5, September/October, 2011.

  • Pierre-Emile Duhamel, Judson Porter, Benjamin Finio, Georey Barrows, David Brooks, Gu-Yeon Wei, and Robert Wood. “Hardware in the Loop for Optical Flow Sensing in a Robotic Bee,” IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), September, 2011.

  • Mark Hempstead, David Brooks, and Gu-Yeon Wei. “An Accelerator-Based Wireless Sensor Network Processor in 130nm CMOS," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Volume 1, No. 2, June, 2011.

  • Peter Bailis, Vijay Janapa Reddi, Sanjay Gandhi, David Brooks, and Margo Seltzer. “Dimetrodon: Processor-Level Preventive Thermal Management via Idle Cycle Injection,” 48th Design Automation Conference (DAC), June, 2011.

  • Wonyoung Kim, David Brooks, and Gu-Yeon Wei. “A Fully-Integrated 3-Level DC/DC Converter for Nanosecond-Scale DVS with Fast Shunt Regulation,” IEEE International Solid-State Circuits Conference (ISSCC-11), Feb. 2011.

  • Krishna Rangan, Michael Powell, Gu-Yeon Wei, and David Brooks. “Achieving Uniform Performance and Maximizing Throughput in the Presence of Heterogeneity,” 17th Annual International Symposium on High-Performance Computer Architecture (HPCA-17), San Antonio, TX, Feb. 2011.

  • Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks. “Voltage Noise in Production Processors,” IEEE Micro's Top Picks in Computer Architecture Conferences, January/February, 2011.

  • Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks. “Voltage Smoothing: Characterizing and Mitigating Voltage Noise in a Production Processor Using Software-Guided Thread Scheduling,” 43rd Annual International Symposium on Microarchitecture (Micro-43), Atlanta, GA, Dec. 2010.

  • Michael Lyons, Mark Hempstead, Gu-Yeon Wei, and David Brooks. “The Accelerator Store Framework for High-Performance, Low-Power Accelerator-based Systems,” IEEE Computer Architecture Letters, July-Dec 2010

  • Benjamin C. Lee and David Brooks. “Applied Inference: Case Studies in Microarchitectural Design,” ACM Transactions on Architectecture and Code Optimization, September 2010. (pdf)

  • Vijay Janapa Reddi, Simone Campanoni, Meeta S. Gupta, Kim Hazelwood, Michael D. Smith, Gu-Yeon Wei, and David Brooks. “Eliminating Voltage Emergencies via Software-Guided Code Transformations,” ACM Transactions on Architectecture and Code Optimization, August 2010. (pdf)

  • Vijay Janapa Reddi, Meeta S. Gupta, Glenn Holloway, Michael D. Smith, Gu-Yeon Wei, David Brooks. “Predicting Voltage Emergencies Using Recurring Program and Microarchitectural Activity,” Proceedings of the IEEE Micro’s Top Picks in Computer Architecture Conferences, January/February, 2010. (pdf)

  • Meeta S. Gupta, Jude Rivers, Pradip Bose, Gu-Yeon Wei and David Brooks. “Tribeca: Design for PVT Variations with Local Recovery and Fine-grained Adaptation,” 42nd Annual International Symposium on Microarchitecture (Micro-42), New York, NY, Dec. 2009. (pdf)

  • Benjamin C. Lee and David Brooks. “Applied Inference: Case Studies in Microarchitectural Design,” ACM: Transactions on Architectecture and Code Optimization. Accepted October 2009. (pdf)

  • Kristen Lovin, Benjamin Lee, Xiaoyao Liang, Gu-Yeon Wei and David Brooks. “Empirical Performance Models for 3T1D Memories,” International Conference on Computer Design (ICCD), Lake Tahoe, CA, Oct. 2009. (pdf)

  • Xiaoyao Liang, Benjamin Lee, David Brooks, Gu-Yeon Wei. “Design and Test Strategies for Microarchitectural Post-fabrication Tuning,” International Conference on Computer Design (ICCD), Lake Tahoe, CA, Oct. 2009. (pdf)

  • Mark Hempstead, Gu-Yeon Wei, and David Brooks. “An Accelerator-based Wireless Sensor Network Processor in 130nm CMOS,” Invited paper. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-09), Grenoble, France, Oct. 2009. (pdf)

  • Michael Lyons and David Brooks. “Design of a Bloom Filter Hardware Accelerator for Ultra Low Power Systems,” International Symposium on Low Power Electronics and Design (ISLPED), San Francisco, CA, August 2009. (pdf)

  • Vijay Janapa Reddi, Simone Campanoni, Meeta S. Gupta, Michael D. Smith, Gu-Yeon Wei, and David Brooks. “Software-Assisted Hardware Reliability: Abstracting Circuit-level Challenges to the Software Stack,” 46th Design Automation Conference (DAC), San Francisco, CA, July 2009. (pdf)

  • Krishna Rangan, Gu-Yeon Wei, David Brooks. “Thread Motion: Fine-Grained Power Management for Multi-Core Systems,” 36th International Symposium on Computer Architecture (ISCA-36), Austin, TX, June 2009. (pdf)

  • Meeta S. Gupta, Vijay Janapa Reddi, Glenn Holloway, Gu-Yeon Wei and David Brooks. “An Event-Guided Approach to Handling Inductive Noise in Processors,” Design, Automation, and Test in Europe Conference (DATE-09), Nice, France, April 2009. (pdf)

  • Vijay Janapa Reddi, Meeta S. Gupta, Krishna K. Rangan, Simone Campanoni, Glenn Holloway, Michael D. Smith, Gu-Yeon Wei, David Brooks. “Voltage Noise: Why It's Bad, and What To Do About It,” 5th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), Palo Alto, CA March 2009. (pdf)

  • Kevin Brownell, A. Durlov Khan, David Brooks, Gu-Yeon Wei. “Place and Route Considerations for Voltage Interpolated Designs,” 10th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 2009. (pdf)

  • Lukasz Strozek, and David Brooks. “Efficient Architectures through Application Clustering and Heterogeneity,” ACM Transactions on Architecture and Code Optimization, Volume 6 , Issue 1, March 2009. (pdf)

  • Vijay Janapa Reddi, Meeta S. Gupta, Glenn Holloway, Michael D. Smith, Gu-Yeon Wei, and David Brooks. “Voltage Emergency Prediction: A Signature-Based Approach To Reducing Voltage Emergencies,” 15th International Symposium on High-Performance Computer Architecture (HPCA-15), Raleigh, NC, February, 2009. Received Best Paper Award. (pdf)

  • Xiaoyao Liang, Gu-Yeon Wei, and David Brooks. “ReVIVaL: Variation Tolerant Architecture Using Voltage Interpolation and Variable Latency,” IEEE Micro’s Top Picks in Computer Architecture Conferences, January/February, 2009.

  • Benjamin C. Lee, Jamison Collins, Hong Wang, and David Brooks. “CPR: Composable Performance Regression for Scalable Multiprocessor Models,” 41st International Symposium on Microarchitecture (Micro-41), Lake Como, Italy, Nov. 2008. Nominated for Best Paper Award. (pdf)

  • Kevin Brownell, Gu-Yeon Wei and David Brooks. “Evaluation of Voltage Interpolation to Address Process Variations,” International Conference on Computer Aided Design (ICCAD), San Jose, CA, Nov. 2008. (pdf)

  • Gu-Yeon Wei, David Brooks, A. Durlov Khan and Xiaoyao Liang. “Instruction-driven Clock Scheduling with Glitch Mitigation,” International Symposium on Low Power Electronics and Design (ISLPED), Bangalore, India, Aug. 2008. Nominated for Best Paper Award. (pdf)

  • Xiaoyao Liang, Gu-Yeon Wei, and David Brooks. “ReVIVaL: Variation Tolerant Architecture Using Voltage Interpolation and Variable Latency,” 35th International Symposium on Computer Architecture (ISCA-35), Beijing, China, June 2008. Selected as one of the Top Picks in Computer Architecture in 2008. (pdf)

  • Mark Hempstead, Gu-Yeon Wei, and David Brooks. “System Design Considerations for Sensor Network Applications,” International Symposium on Circuits and Systems (ISCAS), Seattle, WA, May 2008.

  • Mark Hempstead, Michael J. Lyons, David Brooks and Gu-Yeon Wei. “Survey of Hardware Systems for Wireless Sensor Networks,” ASP Journal of Low Power Electronics, Vol. 4., No. 1, April 2008. (pdf)

  • Benjamin C. Lee and David M. Brooks. “Efficiency Trends and Limits from Comprehensive Microarchitectural Adaptivity,” International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XIII), Seattle, WA, March 2008. (pdf)

  • Meeta S. Gupta, Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei, and David Brooks. “DeCoR: A Delayed Commit and Rollback Mechanism for Handling Inductive Noise in Microprocessors,” 14th International Symposium on High-Performance Computer Architecture (HPCA-14), Salt Lake City, UT, February 2008. (pdf)

  • Benjamin C. Lee and David Brooks. “Roughness of Microarchitectural Design Topologies and its Implications for Optimization,” 14th International Symposium on High-Performance Computer Architecture (HPCA-14), Salt Lake City, UT, February 2008. (pdf)

  • Wonyoung Kim, Meeta Gupta, Gu-Yeon Wei, and David Brooks. “System Level Analysis of Fast, Per-Core DVFS using On-Chip Switching Regulators,” 14th International Symposium on High-Performance Computer Architecture (HPCA-14), Salt Lake City, UT, February 2008. (pdf)

  • Xiaoyao Liang, David Brooks and Gu-Yeon Wei. “A Process-Variation-Tolerant Floating-point Unit with Voltage Interpolation and Variable Latency,” IEEE International Solid-State Circuits Conference (ISSCC-08), Feb. 2008. (pdf)

  • Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, and David Brooks. “Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability,” IEEE MICRO’s Top Picks in Computer Architecture Conferences, January/February, 2008. (pdf)

  • Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei and David Brooks. “Process Variation Tolerant 3T1D-Based Cache Architectures,” 40th International Symposium on Microarchitecture (MICRO-40), Chicago, IL, December 2007. Nominated for CACM special issue consideration by SIGMICRO. Selected as one of the Top Picks in Computer Architecture in 2007. (pdf)

  • Xiaoyao Liang, Kerem Turgay, and David Brooks. “Architectural Power Models for SRAM and CAM Structures Based on Hybrid Analytical/Empirical Techniques,” International Conference on Computer Aided Design (ICCAD-07), San Jose, CA, November 2007. (pdf)

  • Meeta S. Gupta, Krishna K. Rangan, Mike D. Smith, Gu-Yeon Wei and David Brooks. “Towards a Software Approach to Mitigate Voltage Emergencies,” International Symposium on Low Power Electronics and Design, Portland, OR, August 2007. (pdf)

  • Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, and David Brooks. “Process Variation Tolerant Register Files Based on Dynamic Memories,” Workshop on Architectural Support for Gigascale Integration (ASGI-07, held with ISCA-34), June, 2007. (pdf)

  • Wonyoung Kim, Meeta S. Gupta, Gu-Yeon Wei and David Brooks. “Enabling On-Chip Switching Regulators for Multi-Core Processors Using Current Staggering,” Workshop on Architectural Support for Gigascale Integration (ASGI-07, held with ISCA-34), June, 2007.

  • David Brooks, Robert Dick, Russ Joseph, and Li Shang. “Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors,” IEEE Micro Special Issue: Hot Tutorials, May 2007. (pdf)

  • Benjamin C. Lee and David Brooks. “A Tutorial in Spatial Sampling and Regression Strategies for Microarchitectural Analysis,” IEEE Micro Special Issue: Hot Tutorials, May 2007. (pdf)

  • Meeta S. Gupta, Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei, and David Brooks. “Understanding Voltage Variations in Chip Multiprocessors Using a Distributed Power-Delivery Network,” Design, Automation, and Test in Europe Conference (DATE-07), Nice, France, April 2007. (pdf)

  • Benjamin C. Lee, David Brooks, Bronis de Supinski, Martin Schulz, Karan Singh, and Sally McKee. “Methods of Inference and Learning for Performance Modeling of Parallel Applications,” Symposium on Principles and Practice of Parallel Programming, San Jose, CA, March 2007. (pdf)

  • Benjamin C. Lee and David Brooks. “Illustrative Design Space Studies with Microarchitectural Regression Models,” 13th International Symposium on High-Performance Computer Architecture (HPCA-13), Phoenix, AZ, February 2007. (pdf)

  • Xiaoyao Liang and David Brooks. “Mitigating the Impact of Process Variations on CPU Register File and Execution Units,” 39th International Symposium on Microarchitecture (MICRO-39), Orlando, FL, December 2006. (pdf)

  • Xiaoyao Liang and David Brooks. “Microarchitecture Parameter Selection to Optimize System Performance under Process Variation,” International Conference on Computer Aided Design (ICCAD-06), San Jose, CA, November 2006. (pdf)

  • Benjamin C. Lee and David Brooks. “Accurate and Efficient Regression Modeling for Microarchitectural Performance and Power Prediction,” International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XII), San Jose, CA, October 2006. (pdf)

  • Lukasz Strozek and David Brooks. “Efficient Architectures through Application Clustering and Architectural Heterogeneity,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-06), Seoul, Korea, October 2006. (pdf)

  • Mark Hempstead, Gu-Yeon Wei, and David Brooks. “Architecture and Circuit Techniques for Low Throughput, Energy Constrained Systems Across Technology Generations,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-06), Seoul, Korea, October 2006. (pdf)

  • Benjamin C. Lee and David Brooks. “Statistically Rigorous Regression Modeling for the Microprocessor design space,” Workshop on Modeling, Benchmarking, and Simulation (MoBS-06, held in conjunction with ISCA-33), Boston, MA, June 2006. (pdf)

  • Xiaoyao Liang and David Brooks. “Latency Adaptation for Multiported Register Files to Mitigate the Impact of Process Variations,” Workshop on Architectural Support for Gigascale Integration (ASGI-06, held in conjunction with ISCA-33), Boston, MA, June 2006. (pdf)

  • Yingmin Li, Benjamin Lee, David Brooks, Zhigang Hu, Kevin Skadron. “Impact of Thermal Constraints on Multi-Core Architectures,” 10th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronics Systems, San Diego, CA, May 2006. (pdf)

  • Yingmin Li, Benjamin Lee, David Brooks, Zhigang Hu, and Kevin Skadron. “CMP Design Space Exploration Subject to Physical Constraints,” 12th International Symposium on High-Performance Computer Architecture (HPCA-12), February, 2006. (pdf)

  • Qiang Wu, Vijay J. Reddi, Youfeng Wu, Jin Lee, Dan Connors, David Brooks, Margaret Martonosi, and Douglas W. Clark. “Dynamic Compiler Driven Control for Microprocessor Energy and Performance,” IEEE MICRO’s Top Picks in Computer Architecture Conferences, January/February, 2006.

  • Qiang Wu, Vijay Reddi, Youfeng Wu, Jin Lee, Dan Connors, David Brooks, Margaret Martonosi, and Douglas W. Clark. “Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance,” 38th International Symposium on Microarchitecture (MICRO-38), November, 2005. Received Best Paper Award. Selected as one of the Top Picks in Computer Architecture in 2005. (pdf)

  • Yingmin Li, Mark Hempstead, Patrick Mauro, David Brooks, Zhigang Hu, and Kevin Skadron. “Power and Thermal Effects of SRAM vs. Latch-Mux Design Styles and Clock Gating Choices,” International Symposium on Low Power Electronics and Design (ISLPED-05), August 2005. (pdf)

  • Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu-Yeon Wei, and David Brooks. “An Ultra Low Power System Architecture for Wireless Sensor Network Applications,” 32nd International Symposium on Computer Architecture (ISCA-05), June 2005. (pdf)

  • Benjamin C. Lee and David Brooks. “Effects of Pipeline Complexity on SMT/CMP Power-Performance Efficiency,” Workshop on Complexity Effective Design 2005 (WCED2005, held in conjunction with ISCA-32), June 2005. (pdf)

  • Yingmin Li, David Brooks, Zhigang Hu, and Kevin Skadron. “Performance, Energy, and Thermal Considerations for SMT and CMP Architectures,” Eleventh International Symposium on High-Performance Computer Architecture, Feb. 2005. (pdf)

  • Yau Chin, John Sheu, and David Brooks. “Evaluating Techniques for Exploiting Instruction Slack,” International Conference on Computer Design, October 2004. (pdf)

  • Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron, and Pradip Bose. “Understanding the Energy Efficiency of Simultaneous Multithreading,” International Symposium on Low-Power Electronics and Design, August 2004. (pdf)

  • Kim Hazelwood-Cettei and David Brooks. “Eliminating Voltage Emergencies via Microarchitectural Voltage Control Feedback and Dynamic Optimization,” International Symposium on Low-Power Electronics and Design, August 2004. (pdf)

  • Victor Zyuban, David Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N Strenski, and Philip G Emma. “Integrated Analysis of Power and Performance of Pipelined Microprocessors,” IEEE Transactions on Computers, Volume 53, No. 8, August 2004. (pdf)

  • David Brooks, Pradip Bose, and Margaret Martonosi. “Power-Performance Simulation: Design and Validation Strategies,” ACM SIGMETRICS Performance Evaluation Review, March 2004. (pdf)

  • David Brooks, Pradip Bose, Viji Srinivasan, Michael Gschwind, Philip G. Emma, and Michael G. Rosenfield. “New Methodology for Early-stage, Microarchitecture-level Power-performance Analysis of Microprocessors,” IBM Journal of Research and Development, Volume 47, No. 5/6, Nov. 2003. (pdf)

  • Russ Joseph, David Brooks, and Margaret Martonosi. “Control Techniques to Eliminate Voltage Emergencies in High-Performance Processors,” Ninth International Symposium on High-Performance Computer Architecture (HPCA-9), February 2003. (pdf)

  • Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor Zyuban, Philip N Strenski, and Philip G Emma. “Optimizing Pipelines for Power and Performance,” 35th International Symposium on Microarchitecture (MICRO-35), November 2002. Selected as one of the four Best IBM Research Papers in Computer Science, Electrical Engineering and Math published in 2002. (pdf)

  • Pradip Bose, David Brooks, Alper Buyuktosunoglu, Peter Cook, Koushik K. Das, Philip Emma, Michael Gschwind, Hans Jacobson, Tejas Karkhanis, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor Zyuban, David Albonesi, and Sandhya Dwarkadas. “Early-Stage Definition of LPX: A Low Power Issue-Execute Processor Prototype,” Workshop on Power-Aware Computer Systems (PACS2002, held in conjuction with HPCA-8), Cambridge, MA., February 2002. (pdf)

  • Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter Cook, David H. Albonesi. “A Circuit Level Implementation of an Adaptive Issue Queue for Power-Aware Microprocessors,” 11th Great Lakes Symposium on VLSI}, March, 2001. (pdf)

  • David Brooks and Margaret Martonosi. “Dynamic Thermal Management for High-Performance Microprocessors,” 7th International Symposium on High-Performance Computer Architecture (HPCA-7), January 2001. (pdf)

  • David Brooks, Pradip Bose, Stanley E. Schuster, Hans Jacobson, Prabhakar N. Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor Zyuban, Manish Gupta, and Peter W. Cook. “Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors,” IEEE Micro, November/December, 2000. (pdf)

  • David Brooks, John-David Wellman, Pradip Bose, and Margaret Martonosi. “Power-Performance Modeling and Tradeoff Analysis for a High-End Microprocessor,” Workshop on Power-Aware Computer Systems (PACS2000, held in conjunction with ASPLOS-IX), Cambridge, MA., November 2000. (pdf)

  • Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter Cook, and David H. Albonesi. “An Adaptive Issue Queue for Reduced Power at High Performance,” Workshop on Power-Aware Computer Systems (PACS2000, held in conjunction with ASPLOS-IX), Cambridge, MA., November 2000. (ps)

  • David Brooks, Vivek Tiwari, and Margaret Martonosi. “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations,” 27th International Symposium on Computer Architecture (ISCA-27), Vancouver,  Canada, June 2000. (pdf)

  • David Brooks and Margaret Martonosi. “Adaptive Thermal Management for High-Performance Microprocessors,” Workshop on Complexity Effective Design 2000 (WCED2000, held in conjunction with ISCA-27), Vancouver, Canada, June 2000. (pdf)

  • David Brooks and Margaret Martonosi. “Value-Based Clock Gating and Operation Packing: Dynamic Strategies for Improving Processor Power and Performance,” ACM Transactions on Computer Systems., Volume 18, No. 2, May 2000. (pdf)

  • David Brooks and Margaret Martonosi. “Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance,” Fifth International Symposium on High-Performance Computer Architecture (HPCA-5), January 1999. (pdf)

The documents listed above are included by the contributing authors as a means to ensure timely dissemination of scholarly and technical work on a non-commercial basis.  Copyright and all rights therein are maintained by the authors or by other copyright holders, notwithstanding that they have offered their works here electronically. It is understood that all persons copying this information will adhere to the terms and constraints invoked by each author's copyright. These works may not be reposted without the explicit permission of the copyright holder.

 

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