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Harvard Mixed-Signal VLSI |


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Combining Circuits & Architecture to Combat Variability |
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Research Overview Our research activities cover various aspects of mixed-signal VLSI circuits and systems design. We have multiple projects in high-speed links and building blocks that investigate techniques to push performance and reduce power. We are actively pursuing projects related to collaborative software + architecture + circuit techniques to efficiently tackle variability in nanoscale IC technologies in collaboration with architecture and systems groups at Harvard. We also combine circuits and architecture to build high-performance, low-power computing devices via specialization for wireless sensor networks and chip multiprocessors. Links to pdfs of Prof. Gu-Yeon Wei’s updated research narrative and CV. Recent and Upcoming Publications · Software-assisted hardware reliability: Abstracting circuit-level challenges to the software stack · A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS · Thread Motion: Fine-grained power management for multi-core systems · Milligram-scale high-voltage power electronics for piezoelectric microrobots · An Event-Guided Approach to Handling Inductive Noise in Processors · Place and route considerations for voltage interpolated designs · Voltage Noise: Why it’s bad and what to do about it · Voltage emergency prediction: A signature-based approach to reducing voltage emergencies |
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(Last edited: 10 June 2009) |
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News and Events: · See VJ’s paper on software-assisted HW reliability at 2009 DAC in San Francisco, CA · See Hayun’s paper on flash ADC’s for high-speed links at 2009 Symp. on VLSI Circuits in Kyoto, Japan · See Krishna’s paper on Thread Motion at 2009 ISCA in Austin, TX · Congratulations to · See Xiaoyao’s ReVIVaL paper in the Top Picks issue of IEEE micro, Jan/Feb 2009 |