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Harvard Mixed-Signal VLSI |
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Combining Circuits & Architecture to Combat Variability |
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Gu-Yeon Wei
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Research My research group focuses on various aspects of mixed-signal VLSI circuits and system design. We have multiple projects in high-speed links and building blocks that investigate techniques to push performance and reduce power. We are actively pursuing projects related to collaborative software + architecture + circuit techniques to efficiently tackle variability in nanoscale IC technologies in collaboration with architecture and systems groups at Harvard. We also investigate how to combine circuits and architecture to build ultra-low-power computing devices for wireless sensor networks. A narrative of my research activities can be found here and my updated CV here. Recent and Upcoming Publications · An 8x5 Gb/s source-synchronous receiver with clock generator phase error correction · A 12.5-Gbps, 7-bit transmit DAC with 4-tap LUT-based equalization in 0.13um CMOS · Instruction-driven clock scheduling with glitch mitigation · A high-throughput maximum a posteriori probability detector · ReVIVaL: A variation tolerant architecture using voltage interpolation and variable latency · An 8x3.2Gb/s parallel receiver with collaborative timing recovery · A process-variation-tolerant floating-point unit with voltage interpolation and variable latency
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Gu-Yeon Wei MD 333 33 Oxford St. Cambridge, MA 02138 guyeon {at} eecs.harvard.edu |
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Contact Information |
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Carol Harlow MD 347 33 Oxford St. Cambridge, MA 02138 harlow {at} seas.harvard.edu |
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Administrative Assistant |
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(Last edited: 7 June 2008) |
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Associate Professor of Electrical Engineering |