2008
· A high-throughput maximum a posteriori probability detector
Ruwan Ratnayake, Aleksandar Kavcic and Gu-Yeon Wei
IEEE Journal of Solid-State Circuits, accepted for Aug. 2008. (pdf soon)
· A highly-digital MDLL-based clock multiplier that leverages a self-scrambling time-to-digital converter to achieve sub-picosecond jitter performance
Belal M. Helal, Matthew Z. Straayer, Gu-Yeon Wei and Michael H. Perrott
IEEE Journal of Solid-State Circuits, in press, April 2008. (pdf soon)
· Survey of hardware systems for wireless sensor networks (Invited)
Mark Hempstead, Michael J. Lyons, David Brooks and Gu-Yeon Wei
ASP Journal of Low Power Electronics, Vol. 4., No. 1, 2008. (pdf soon)
· ReVIVaL: A variation tolerant architecture using voltage interpolation and variable latency
Xiaoyao Liang, Gu-Yeon Wei and David Brooks
International Symposium on Computer Architecture (ISCA-35), June 2008. (pdf)
· Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei and David Brooks
IEEE Micro Top Picks, Feb. 2008. (pdf available soon)
· An 8x3.2Gb/s parallel receiver with collaborative timing recovery
Ankur Agrawal, Pavan Hanumolu and Gu-Yeon Wei
IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2008. (pdf)
· A process-variation-tolerant floating-point unit with voltage interpolation and variable latency
Xiaoyao Liang, David Brooks and Gu-Yeon Wei
IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2008. (pdf)
· System level analysis of fast, per-core DVFS using on-chip switching regulators
Wonyoung Kim, Meeta S. Gupta, Gu-Yeon Wei and David Brooks
14th International Symposium on High-Performance Computer Architecture (HPCA-14), Feb. 2008. (pdf)
· DeCoR: A delayed commit and rollback mechanism for handling inductive noise in processors
Meeta S. Gupta, Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei and David Brooks
14th International Symposium on High-Performance Computer Architecture (HPCA-14), Feb. 2008. (pdf)
· A wide-tracking range clock and data recovery circuit
Pavan K. Hanumolu, Gu-Yeon Wei and Un-Ku Moon
IEEE Journal of Solid-State Circuits, Feb. 2008. (pdf)
· A sub-picosecond resolution 0.5-1.5GHz digital-to-phase converter
Pavan K. Hanumolu, Vlodomir Kratyuk, Gu-Yeon Wei and Un-Ku Moon
IEEE Journal of Solid-State Circuits, Feb. 2008. (pdf)
2007
· Process variation tolerant 3T1D-based cache architectures
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei and David Brooks
40th International Symposium on Microarchitecture (MICRO-40), Dec. 2007. (pdf)
· A bit-node centric architecture for low-density parity-check decoders
Ruwan Ratnayake, Erich F. Haratsch and Gu-Yeon Wei
IEEE Global Communications Conference (Globecom), Nov. 2007. (pdf)
· A high-throughput maximum a posteriori probability detector
Ruwan Ratnayake, Aleksander Kavcic and Gu-Yeon Wei
IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007. (pdf)
· Digitally-enhanced phase-locking circuits
Pavan K. Hanumolu, Gu-Yeon Wei, Un-Ku Moon and Karti Mayaram
IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007. (pdf)
· A comprehensive phase-transfer model for delay-locked loops
Jim Burnham, Gu-Yeon Wei, Chih-Kong Ken Yang and Haitham Hindi
IEEE Custom Integrated Circuits Conference (CICC), Sept. 2007. (pdf)
· Serial sum-product architecture for low-density parity-check codes
Ruwan Ratnayake, Erich F. Haratsch and Gu-Yeon Wei
International Conference in Computer Communications and Networks, Aug. 2007. (pdf)
· Towards a software approach to mitigate voltage emergencies
Meeta S. Gupta, Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei and David Brooks
International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2007. (pdf)
· A low jitter 1.6 GHz multiplying DLL utilizing a scrambling time-to-digital converter and digital correlation
Belal M. Helal, Matthew Z. Straayer, Gu-Yeon Wei and Michael H. Perrott
IEEE Symposium on VLSI Circuits (VLSI), June 2007. (pdf)
· Process variation tolerant register files based on dynamic memories
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei and David Brooks
Workshop on Architectural Support for Gigascale Integration (ASGI-07, at ISCA-34), June 2007. (pdf)
· Enabling on-chip switching regulators for multi-core processors using current staggering
Wonyoung Kim, Meeta S. Gupta, Gu-Yeon Wei and David Brooks
Workshop on Architectural Support for Gigascale Integration (ASGI-07, at ISCA-34), June, 2007. (pdf)
· Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
Meeta S. Gupta, Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei and David Brooks
10th Design, Automation, and Test in Europe Conference (DATE-10), April 2007. (pdf)
2006
· Architecture and circuit techniques for low throughput, energy constrained systems across technology generations
Mark Hempstead, Gu-Yeon Wei and David Brooks
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-06), Oct. 2006. (pdf)
· A 1.6Gbps digital clock and data recovery circuit
Pavan K. Hanumolu, Gu-Yeon Wei and Un-Ku Moon
IEEE Custom Integrated Circuits Conference (CICC), Sept. 2006. (pdf)
· Adaptive-bandwidth mixing PLL/DLL based multi-phase clock generator for optimal jitter performance
Amber H. Tan and Gu-Yeon Wei
IEEE Custom Integrated Circuits Conference (CICC), Sept. 2006. (pdf)
· Phase mismatch detection and compensation for PLL/DLL based multi-phase clock generator
Amber H. Tan and Gu-Yeon Wei
IEEE Custom Integrated Circuits Conference (CICC), Sept. 2006. (pdf)
· PulseNet: A parallel flash sampler and digital processor IC for optical SETI
Andrew Howard, Gu-Yeon Wei, William J. Dally and Paul Horowitz
IEEE Custom Integrated Circuits Conference (CICC), Sept. 2006. (pdf)
· A wide tracking range 0.2-4Gbps clock and data recovery circuit
Pavan K. Hanumolu, Gu-Yeon Wei and Un-Ku Moon
IEEE Symposium on VLSI Circuits (VLSI), June 2006. (pdf)
· A sub-picosecond resolution 0.5-1.5GHz digital-to-phase converter
Pavan K. Hanumolu, Vlodomir Kratyuk, Gu-Yeon Wei and Un-Ku Moon
IEEE Symposium on VLSI Circuits (VLSI), June 2006. (pdf)
· Equalizers for high-speed serial links
Pavan K. Hanumolu, Gu-Yeon Wei and Un-Ku Moon
Design of High-Speed Communication Circuits (Edited by Ramesh Harjani),
World Scientific Publishing Company, Vol. 38, 2006. (pdf)
2005 and prior years
· Equalizers for high-speed serial links
Pavan K. Hanumolu, Gu-Yeon Wei and Un-Ku Moon
Int’l Journal of High Speed Electronics, Vol. 15, No. 2, 2005. (pdf)
· An ultra low power system architecture for wireless sensor network applications
Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu-Yeon Wei and David Brooks
32nd International Symposium on Computer Architecture (ISCA-05), June 2005. (pdf)
· Exploring the Design Space of Power-Aware Opto-Electronic Network Systems
Xuning Chen, Li-Shiuan Peh, Gu-Yeon Wei, Y.-K. Huang and Paul Prucnal
International Symposium on High-Performance Computer Architecture (HPCA-11), Feb. 2005. (pdf)
· A portable, low-power, wireless two-lead EKG system
Thaddeus R.F. Fulford-Jones, Gu-Yeon Wei and Matt Welsh
26th IEEE EMBS Annual International Conference, Sept. 2004. (pdf)
· A mixed PLL/DLL architecture for low jitter clock generation
Yong-Cheol Bae and Gu-Yeon Wei
IEEE International Symposium on Circuits and Systems (ISCAS), Oct. 2004. (pdf)
· Pipelined parallel architecture for high throughput MAP detectors
Ruwan Ratnayake, Gu-Yeon Wei and Aleksander Kavcic
IEEE International Symposium on Circuits and Systems (ISCAS), Oct. 2004. (pdf)
· Jitter in high-speed serial and parallel links
Pavan K. Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei and Un-Ku Moon
IEEE International Symposium on Circuits and Systems (ISCAS), Oct. 2004. (pdf)
· Analysis of PLL clock jitter in high-speed serial links
Pavan K. Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei and Un-Ku Moon
IEEE Transactions on Circuits and Systems II (TCAS-II), vol. 50, no. 11, Nov. 2003. (pdf)
· Design of CMOS adaptive-bandwidth PLL/DLLs: A general approach
Jaeha Kim, Mark A. Horowitz, Gu-Yeon Wei
IEEE Transactions on Circuits and Systems II (TCAS-II), vol. 50, no. 11, Nov. 2003. (pdf)
· Adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS
John T. Stonick, Gu-Yeon Wei, Jeff Sonntag, Daniel K. Weinlader
IEEE Journal of Solid-State Circuits, vol. 38, no. 3, March 2003. (pdf)
· A 500-MHz MP/DLL clock generator for a 5-Gb/s backplane transceiver in 0.25-μm CMOS
Gu-Yeon Wei, John T. Stonick, Daniel K. Weinlader, Jeff Sonntag, Shawn Searles
IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2003. (pdf)
· Energy-efficient design of high-speed links
Gu-Yeon Wei, Mark .A. Horowitz, Jaeha Kim
Power Aware Design Methodologies
Kluwer Academic Publishers, contributed chapter, June 2002. (pdf)
· An Adaptive PAM-4 5Gb/s Backplane Transceiver in 0.25um CMOS
Jeff Sonntag, John T. Stonick, Jim Gorecki, Bill Beale, Bill Check, Xue-Mei Gong, Joseph Guiliano, Kyong Lee, Bob Lefferts, David Martin, Un-Ku Moon, Amber Sengir, Steve Titus, Gu-Yeon Wei, Daniel K. Weinlader and Yaohua Yang
IEEE Custom Integrated Circuits Conference (CICC), May 2002. (pdf)
· A variable-frequency parallel I/O interface with adaptive power-supply regulation
Gu-Yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos and Mark A. Horowitz
IEEE Journal of Solid-State Circuits, vol. 35, no. 11, November 2000. (pdf)
· Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers
Stefanos Sidiropoulos, Dean Liu, Jaeha Kim, Gu-Yeon Wei, Mark A. Horowitz
IEEE Symposium on VLSI Circuits (VLSI), June 2000. (pdf)
· A high-performance variable frequency I/O with adaptive power supply regulation
Gu-Yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos and Mark A. Horowitz
IEEE International Solid-States Circuits Conference (ISSCC), Feb. 2000. (pdf)
· A high-performance variable frequency I/O with adaptive power supply regulation
Gu-Yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos and Mark A. Horowitz
IEEE 2000 Mesa Computer Elements Workshop, Low-Power Design Contest, Jan. 2000. (link)
· A fully digital energy efficient adaptive power supply regulator
Gu-Yeon Wei and Mark A. Horowitz
IEEE Journal of Solid-State Circuits, vol. 34, no. 4, April 1999. (pdf)
· A low power switching power supply for self-clocked systems
Gu-Yeon Wei and Mark A. Horowitz
Low-Power CMOS Design
IEEE Press, contributed paper, 1998. (link)
· A low power switching power supply for self-clocked systems
Gu-Yeon Wei and Mark A. Horowitz
IEEE International Symposium on Low Power Electronics and Design (ISLPED), Aug. 1996. (pdf)
· Oxidation enhanced dopant diffusion in separation by implantation by oxygen silicon-on-insulator material
Scott W. Crowder, Peter B. Griffen, C.J. Hsieh, Gu-Yeon Wei, James D. Plummer, L.P. Allen
Applied Physics Letters, June 1994.
PhD Dissertations
· Design of noise-robust clock and data recovery using an adaptive-bandwidth mixed PLL/DLL
Amber H. Tan
Ph.D. Dissertation, Harvard University, Division of Engineering and Applied Sciences, Nov. 2006. (pdf)
· Energy-efficient IO interface design with adaptive power-supply regulation
Gu-Yeon Wei
Ph.D. Dissertation, Stanford University, Department of Electrical Engineering, June 2001. (pdf)
