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Semiconductor = Industry=20 Initiatives Seek to Capture EE Student = Interest,=20 Increase Retention

by David Ferrell

The = semiconductor=20 industry is a leader in innovation and a = major=20 contributor to improvements in = productivity and=20 the gross national product. The amazing = leaps we=20 have made in technology have a common = thread at=20 their core: talented, creative engineers = able to=20 find new ways to add incredible power, = speed and=20 functionality to the thousands of chip = designs=20 and applications we see all around us = every day.=20 The Semiconductor Industry Association's = (SIA)=20 member companies are concerned that the = supply=20 of qualified electrical engineering (EE) = graduates will not be adequate to meet = the=20 industry's workforce demands in the = years ahead.=20 Enrollments in the critical EE major are = showing=20 signs of declining at a number of = schools;=20 underserved populations are not well = represented=20 in this exciting and rewarding = profession;=20 competition from other countries is = increasing=20 rapidly; and the nation's retention rate = for EEs=20 is below 40 percent =97 even worse for = underserved=20 populations.

SIA = believes that the=20 best way to increase the quality and = supply of=20 graduating EEs is to increase the = retention rate=20 of students already enrolled in the EE = major.=20 After discussions with a number of = leading=20 institutions, SIA has concluded that it = is=20 possible to increase the success and = retention=20 of students in years one and two by = providing=20 them with focused support systems, which = can=20 take many forms, including: mentors, = study=20 partners, study teams, resource rooms, = faculty=20 partners and pre-college = camps.

SIA and=20 some heavy hitters from the nation's = chip-making=20 industry are lending their support to = two=20 important initiatives aimed at reversing = slipping EE enrollments and increasing = retention=20 among students already enrolled in EE=20 majors.

The SoC Design=20 Challenge =97=20 IC = Systems Design=20 at the Leading Edge

The = Semiconductor=20 Research Corporation (SRC) and SIA = announced in=20 November 2004 their co-sponsorship of = the SoC=20 Design Challenge, a contest open to = North=20 American university students and faculty = to=20 create novel, low-power system-on-chip = (SoC)=20 designs that demonstrate the value of = greater=20 systems=20 integration in integrated circuit = design. Total=20 prizes amounting to $75,000 will be = awarded to=20 winning submissions. Finalists will have = an=20 opportunity to have MOSIS=20 fabricate their designs by in an = advanced=20 180-nanometer CMOS (complementary = metal-oxide=20 semiconductor) technology. Major partner = companies providing funding for the = fabrication=20 phase of the challenge include: AMD, = AMI, Analog=20 Devices, Cadence, Freescale, IBM, Intel, = National Semiconductor and Texas=20 Instruments.

The = SRC/SIA SoC=20 Design Challenge is a novel approach to=20 stimulating creative thinking by the = future=20 innovators of the semiconductor = industry. The=20 "killer chips" of the future will be = designed by=20 talented individuals who are in = engineering=20 schools throughout North America today. = The SoC=20 Design Challenge goalto stimulate = creative=20 thinking among the future leaders of our = industry. System-on-chip designs have = become=20 increasingly important in our = never-ending quest=20 to put a maximum of functionality in the = minimum=20 amount of silicon "real estate." SoC = designs=20 make use of today=92s most advanced = technologies=20 to offer higher-performance, lower-power = consumption and lower system = costs.

=93This = contest will=20 provide the winners with a unique = opportunity to=20 see their designs turned into working = silicon=20 using an advanced 180-nanometer = technology,=94=20 according to Dale Edwards, Design = Research=20 Programs Manager with SRC. =93A major = goal of the=20 SoC Design Challenge is to stimulate = greater=20 interest in integrated circuit design = careers=20 among electrical engineering students,=20 especially among those skilled in analog = and=20 digital signal processing technologies. = These=20 are areas where our member companies = report a=20 major challenge in finding qualified = candidates=20 for job openings.=94

SRC/SIA = will conduct=20 the contest in two phases, with prizes = awarded=20 to the top three contestants in each = phase. In=20 Phase One, contestants will submit chip = designs=20 using novel architectures or subsystems = that=20 exploit the advantages of greater = systems=20 integration. Cash prizes of $7,000, = $5,000 and=20 $3,000 will be awarded to the first, = second and=20 third place winners. In Phase Two, the = top five=20 entries from Phase One will complete = their=20 layouts and submit their designs for = fabrication=20 on a 180-nanometer, mixed-signal CMOS = process at=20 MOSIS. The top winners will be awarded = cash=20 prizes of $25,000, $15,000 and $10,000 = for=20 first, second and third places. All = monetary=20 prizes will go to the winning teams=92 = EE=20 departments to help further studies in = this=20 important area.

=93A major goal = is to=20
stimulate greater interest in = integrated=20 circuit design careers among electrical=20 engineering students, especially among = those=20 skilled in analog and digital signal = processing=20 technologies. These are areas where our = member=20 companies report a major challenge in = finding=20 qualified candidates for job=20 openings.=94

=93Every = aspiring IC=20 design engineer dreams of seeing his or = her=20 creative ideas translated into real = silicon,=94=20 said Edwards. =93The SRC/SIA SoC Design = Challenge=20 offers a unique opportunity to make = these dreams=20 come true.=94

Complete = contest=20 rules and more information can be found = at the=20 SRC and SIA websites: http://www.src.org/So= C_contest/default.asp=20 and www.sia-online.= org/eve_event.cfm?ID=3D167.

SRC/SIA = presented=20 awards to this year's Phase One Winners = at=20 Techcon in Portland, Ore., on 26 = October. A=20 brief description of the winning teams=20 follows:

Team = #28=20 (University of Virginia), led by = Professor=20 Mircea Stan, took first place in Phase = One with=20 its entry, "An SRAD Image Processor as a = Reconfigurable, Temperature-Aware SoC = Designed=20 for Low-Power Operation." This is a = design of a=20 low-power ultrasound system on a chip = for=20 portable applications using an efficient = algorithm to increase signal to noise=20 performance.

Team = #36=20 (Harvard University), led by Professor = Gu-Yeon=20 Wei, placed second for its entry, = "Design and=20 Implementation of an Ultra-Low Power=20 Event-Driven System Architecture for = Sensor=20 Network Applications." This ultra-low = power=20 design targets extreme energy efficiency = for use=20 in remote sensor = applications.

Team = #38=20 (Michigan State University), led by = Professor=20 Peixin Zhong, came in third in the = competition=20 with its entry, "Adaptive Sensor Network = Platform Chip." This design creates a = platform=20 with flexible sensor interface suitable = for=20 scanning an array of inputs of different = types=20 for a broad range of = applications.

Team = #7=20 (University of Tennessee-Knoxville) is = led by=20 Professor Don Bouldin and its design is=20 entitled, "A System-on-Chip with = Enhanced=20 Reliability and Flexibility."

Team = #27=20 (Tufts University) is led by Professor = Sameer=20 Sonkusale and its design is "An Active = Pixel=20 Sensor Based Camera-On-Chip with Global = and=20 Local Spatial-Temporal Image=20 Processing."

The SIA Stay=20 Tech Program =97 Keeping Tomorrow=92s = Engineers In=20 School Today

In May, = SIA=20 awarded grants to five leading = engineering=20 schools to support innovative pilot = programs=20 to improve the retention and success of = year-one=20 and year-two students enrolled in their=20 engineering schools. The Stay Tech = program is an=20 offshoot of SIA's efforts to improve the = number=20 and quality of EEs graduating from the = nation's=20 engineering schools. =93Electrical = engineering is=20 a very demanding major,=94 said SIA = President=20 George Scalise. =93It is not surprising = that the=20 attrition rate is high. The Stay Tech = program=20 has the potential of achieving a very = high=20 return on investment. The creative = retention=20 programs developed by these five = engineering=20 schools would work anywhere, and I = believe they=20 will demonstrate that much can be = accomplished=20 without spending a lot of money. Even a = modest=20 reduction in the drop-out rate would = have a very=20 large and rapid impact on the number of=20 engineers available to meet the future = needs of=20 our industry.=94

A panel = of judges,=20 composed of representatives from SIA and = other=20 Stay Tech sponsor companies, evaluated=20 retention-improvement submissions from = 43=20 schools this year and awarded five = grants of=20 $20,000 each to the University of=20 California-Riverside, the University of = the=20 Pacific, Rochester Institute of = Technology,=20 North Carolina A&T, and Boise State=20 University. The judges' determinations = were=20 based on the following = criteria:

Impact

What is = the=20 anticipated impact of the proposal in = increasing=20 EE retention in years one and two, = including=20 relevant metrics?
=20
What = specific plans=20 and programs are to be executed? How = will the=20 proposed improvements help keep current = EEs in=20 the major and on track for graduation? = What will=20 be done to increase participating = students'=20 overall academic performance = ?
=20
How will = the=20 proposal increase the chances for = success for=20 those students = involved?
=20
What is = the=20 institution's commitment level to the=20 anticipated results of the proposal? = (provide=20 follow-on measurements of the programs=20 results)

Underserved=20 Populations

How will = the=20 proposal address underserved populations = in the=20 major?
=20
Specific = proposal=20 elements that target underserved = populations=20 should be highlighted in detail=20

Sponsor Access to=20 Students

How will = the sponsor=20 companies have access to the students = involved=20 in the program for possible assistance,=20 communications and support, including=20 consideration for employment=20 opportunities?

Coordination and=20 Execution

How will = the the=20 proposal's elements be coordinated with = other=20 organizations and programs within the=20 institution to provide leverage and = maximum=20 benefit?
=20
What is = the strategy=20 for launching, communicating and = marketing the=20 program to ensure maximum positive = results and=20 visibility? =

SIA=92s = Workforce=20 Strategy Committee (http://www.sia-online.org/),=20 IBM Corporation (http://www.ibm.com/),=20 LSI Logic (http://www.lsilogic.com/),=20 National Semiconductor Corporation (http://www.national.com/),=20 and Xilinx Corporation (http://www.xilinx.com/)=20 are the Stay Tech Program's primary=20 sponsors.

For more = information=20 on the Stay Tech program, visit:
www.sia-online.= org/eve_event.cfm?ID=3D172=20

E-mail this = page
to a=20 friend

Tell = us what you thought of this=20 = article

David = Ferrell is=20 Director of SIA's Workforce=20 Strategy.=20 Comments may be submitted to todaysengineer@ieee.org.<= /FONT>

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