Depending on the processor type in use, this area may appear automatically at some other address in virtual memory, or may need to be mapped into kernel virtual memory using the MMU. For more information, click here.
The last slot, slot 31, is always occupied by the bus controller card. Its mapped memory area is divided into two parts. The upper half (32k) is reserved for mapping a boot ROM, which has no published entry points, supplies no services besides system startup, and may or may not actually be present. The lower half (also 32k) is split into 32 1k regions, each of which maps configuration data about its corresponding slot. The last such region refers to the bus controller card itself, and has some additional registers.
The physical address of the config region for slot N can be computed as LAMEBASE+(0x10000*31)+(0x400*N). Again, the virtual address depends on the processor type.
Each of these config regions contains the following fields:
Name Offset Description VID 0x00-0x03 Vendor ID of device DID 0x04-0x07 Device type ID DRL 0x08-0x0b Device revision level 0x0c-0x3ff Reserved
Vendor IDs defined are as follows:
If no card is present, the other fields in the region may contain invalid values, and references to that slot's mapping area will (normally) cause memory bus errors.
Value Organization 0 No card present 1 CS161 Course Staff
The device type IDs and revision levels are defined by the vendors.
Offsets 512-1023 (0x200-0x3ff) of the bus controller's own configuration region are mapped to the bus controller's own registers. For the CS161 revision 1 bus controller (VID 1, DID 1, DRL 1) these registers are:
RAMSZ reports the system main board configuration. Writes are rejected. Where the physical RAM appears in the physical address space, and whether it's contiguous (and if not, where the gaps are) depends on the processor type.
Name Offset Description RAMSZ 0x200-0x203 Size of physical RAM in bytes IRQS 0x204-0x207 Mask of slots presently interrupting PWR 0x208-0x20b Power enable register 0x20c-0x3ff Reserved
The IRQS register holds a 1 for each slot that is presently asserting its IRQ line. Writes to IRQS are rejected; interrupts should be cleared on the devices generating them. Bit 0 represents slot 0, etc. Thus bit 31 is the bus controller's bit.
The PWR register switches the system off if the magic value 0xfee1dead is written into it. Other writes have no effect, and reading produces undefined results.