My research focusses on understanding the inductive noise problem in microprocessors and design solutions at the micro-architectural level to handle inductive noise problem with minimal performance impact.

Increases in peak current draw and reductions in the operating voltages of processors continue to amplify the importance of dealing with voltage fluctuations in processors. Prior work in this domain has been either focussed on circuit- or architectural-level techniques. We aim to provide a more holistic solution to this problem, by understanding the complex interaction between the underlying power-delivery subsystem, the micro-architecture and the application. We believe that such a solution would help in designing the systems for eliminate the need for highly conservative designs and hence provide performance as well as robustness guarantees.

Distributed power-delivery susbsystem

Recent efforts to address microprocessor power dissipation through aggressive supply voltage scaling and power management require that designers be increasingly cognizant of power supply variations. We have proposed a fine-grain, parameterizable model for power-delivery networks that allows system designers to study localized, on-chip supply fluctuations in high-performance microprocessors. Using this model, we analyze voltage variations in the context of next-generation chip-multiprocessor (CMP) architectures using both real applications and synthetic current traces. Activity of distinct cores in CMPs present several new design challenges when considering power supply noise.

Dynamic-optimization solution for handling inductive noise