Fast, Per-Core DVFS using Fully Integrated Voltage Regulators
Modern SoCs use dynamic voltage and frequency scaling (DVFS) to save power by scaling both the voltage and frequency according to CPU demand. However, the effectiveness of current power management techniques are limited by the following.
1) DVFS: shared voltage across multiple cores/IP blocks (Figure 1)
2) DVFS: slow voltage scaling time (Figure 2)
3) Power Gating: slow to turn on from off-state, lose data when powered off
Fig 1. Per-core voltage reduces wasted energy due to shared voltage
One way to enable per-core voltage control is to use multiple off-chip switching DC-DC converters, but the bulk of off-chip components make this solution expensive.
Instead, we propose to design voltage regulators small enough to integrate on the same die as the SoC. Multiple integrated voltage regulators (IVR) can be duplicated for per-core voltage control. IVRs offer 20ns/V voltage scaling time, which is 500x faster than the 10us/V of conventional off-chip DC-DC converters, enabling fast, per-core DVFS. This allows the SoC to reduce the voltage during relatively short time periods, i.e. ~200 cycles while waiting for a L2 cache miss to return, or boost the voltage to speedup the execution of critical sections.
Fig 2. IVRs enable 20ns/V voltage scaling, which is 500x faster than conventional 10us/V scaling, to reduce wasted power.
To maximize the benefits of IVRs, it is critical to minimize conversion loss and on-die area overhead while providing a wide range of output voltage for DVFS. Linear regulators incur larger conversion loss as output voltage is reduced for DVFS. Widely used buck converters (inductor-based) require large inductors, which is especially problematic for on-die integration. We presented a 3-level IVR that enables a smaller on-chip spiral inductor (1nH) compared to a buck converter [ISSCC '11].
Although various on-chip regulator overheads eat into benefits of fast, per-core DVFS, architectural investigations demonstrate the potential for significant energy savings, especially for memory-bound workloads [HPCA '08][ASGI '07].
IVRs also enable fewer PCB components compared to only using conventional off-chip DC-DC converters (Figure 3).
Power management IC (PMIC) chips in handsets provide multiple voltages to the SoC using multiple inductors and capacitors on the PCB.
For example, the Tegra 2 SoC uses one voltage for the high-frequency ARM cores,
while using a second voltage for other IP blocks running at lower frequencies
[link].
Using IVRs, the SoC receives a single voltage and steps it down to multiple voltage within the chip, reducing the number of
inductors required on the PCB. Since IVRs can provide tight voltage regulation, less regulation is needed on V3 (2V),
allowing fewer capacitors on the PCB.
Fig 3. Power delivery path of conventional and SoC using IVRs. IVRs enable fewer pcb components.
In conclusion, IVRs have the potential to 1) reduce power of multi-core SoCs, 2) reduce the number of PCB components and 3) enable lighter, thinner portable electronics. IVRs can be used in high-performance processors and FPGAs as well as low-power SoCs.