HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs

Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy Jones, Gu-Yeon Wei, David Brooks

International Symposium on Computer Architecture (ISCA), June, 2014

Data dependences in sequential programs limit parallelization because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual dependences counteract the benefits of parallelization. To address these challenges, we propose a lightweight architectural enhancement co-designed with a parallelizing compiler, which together can decouple communication from thread execution. Simulations of these approaches, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85x performance speedup for six SPEC CINT2000 benchmarks.

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 author = {Campanoni, Simone and Brownell, Kevin and Kanev, Svilen and Jones, Timothy M. and Wei, Gu-Yeon and Brooks, David},
 title = {{HELIX-RC}: An Architecture-compiler Co-design for Automatic Parallelization of Irregular Programs},
 journal = {ISCA},
 issue_date = {June 2014},
 volume = {42},
 number = {3},
 month = jun,
 year = {2014},
 issn = {0163-5964},
 pages = {217--228},
 numpages = {12},
 url = {http://doi.acm.org/10.1145/2678373.2665705},
 doi = {10.1145/2678373.2665705},
 acmid = {2665705},
 publisher = {ACM},
 address = {New York, NY, USA},