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News and Activities

Xiaoyao's ReVIVaL paper was accepted by premier architecture conference ISCA 2008. He will present his work in Beijing.

Xiaoyao's FPU prototype chip met all the design specs and he presented his work at premier circuit conference ISSCC 2008.

Xiaoyao's 3T1D cache paper was selected into Micro Top Picks, awarded to 10 most industry relevant architecture papers in 2007.

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I am a Ph. D student in the School of Engineering and Applied Sciences at Harvard University. My research interests include computer architectures and VLSI design. I am currently working with Prof. David Brooks and Prof. Gu-Yeon Wei

Before I came to Harvard, I got my Bachelors degree from Fudan Univeristy in China, and Masters degree from Stony Brook University at New York. I also spent three years working as a full time digital IC and ASIC designer at several companies. 

My current research focuses on joint computer architecture, CAD, and circuit solutions that are aware of upcoming design challenges such as process, temperature and voltage variations in nano-scale era. I am also looking for novel methodologies for early stage performance and power modeling of modern microprocessors. 

Looking forward, I hope to conduct advanced research in the area of variation tolerant circuits and microarchitecture, variation aware and self-adaptable embedded systems, VLSI circuits, architectures and EDA tools for the nano-scale computing systems, multi-core architectures and underlying application specific circuits for biology and scientific applications

 

 

Computer Architecture and VLSI Design Laboratory, SEAS, Harvard University, Cambridge, MA 02138
Tel: 617-496-0141 | Email: xliang@fas.harvard.edu

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