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Administrivia Course syllabus Tutorials Getting started with CAD Corner Analysis Editing a Layout Checking Design Rules (DRC) Checking Layout Versus Schematic (LVS) Extracting Parasitics (PEX) Simulating Post-PEX Netlists Verilog According to Lukasz Verilog Two-Phase Clocking Guide Verilog According to Tom Verilog Test Bench Primer Synthesis Placement and Routing Simulation with Vectors from Verilog Guides Synthesis Simulation